Comparator tracking control scheme with dynamic window length

ABSTRACT

A comparator tracking scheme for an analog-to-digital converter (ADC) may implement a dynamic window size by varying, over time, a number of comparators powered up to convert an analog input signal to a digital output signal. A comparator-tracking scheme may be implemented, for example, in a controller coupled to a plurality of comparators in an ADC. For example, the controller may determine a window size for the ADC and determine a window position for the ADC. The controller may then activate comparators of the ADC within a window centered at the window position and having a width of the window size. The controller may determine a window size by analyzing an output of a filter. When the filter output indicates a rapidly changing analog input signal, the controller may dynamically increase a window size of the ADC, which may increase a number of comparators powered on.

FIELD OF THE DISCLOSURE

The instant disclosure relates to electronic circuits. Morespecifically, this disclosure relates to analog-to-digital converters(ADC).

BACKGROUND

Analog-to-digital converters (ADCs) convert analog signals to discretedigital signals for processing by digital electronics. For example, anADC may be used to convert an analog audio input from a microphone to adigital signal for processing and manipulation by a digital processor,such as a microprocessor or a digital signal processor (DSP). Oneexample of a conventional ADC is shown in FIG. 1.

An ADC 100 may receive an input signal, V_(in), for conversion to adigital signal. The input signal, V_(in), may range, for example,between 0 and 5 Volts. The ADC may convert the input signal, V_(in), toa digital output signal, OUT, through a plurality of comparators 102A-N.The digital output signal, OUT, may have N bits corresponding to thenumber of comparators 102A-N. Each of the comparators 102A-N compare theinput signal, V_(in), to a reference level that is a fraction of areference input, V_(ref), defined by resistors 104A-N. For example, whenthe input signal, V_(in), ranges from 0 to 5 Volts, and there are fourcomparators, the comparator 102A may compare the input voltage, V_(in),to 3.75 Volts, the comparator 102B may compare the input signal, V_(in),to 2.5 Volts, the comparator 102C may compare the input signal, V_(in),to 1.25 Volts, and the comparator 102N may compare the input signal,V_(in), to 0 Volts. Each of the comparators 102A-N may output a zerovalue if the input signal, V_(in), is not higher than 3.75, 2.5, 1.25,and 0 Volts, respectively. Likewise, each of the comparators 102A-N mayoutput a one value if the input signal, V_(in), is higher than 3.75,2.5, 1.25, and 0 Volts, respectively. Thus, when the input signal,V_(in), is 3.0 Volts, the output digital signal, OUT, would be “0111.”Accuracy may be improved in the ADC 100 by, for example, increasing thenumber of comparators 102A-N.

In the example provided above, each of the comparators 102A-N iscontinuously comparing the input signal, V_(in), to a reference level.Thus, each of the comparators 102A-N is consuming power, despite thefact that the outputs of some of the comparators 102A-N may rarelychange. In the example described above, the input signal, V_(in), mayrange between 0 and 5 Volts, but generally remains around 2.5-3.0 Volts.For such a signal, the comparators 102A and 102B may be sufficient forpart of the time to generate the digital output signal, OUT, and thecomparators 102C and 102D may be powered down.

Conventional tracking ADCs are one type of ADC that focuses onconversion of a small sampling region. A tracking ADC may activatecomparators around a region of interest and power down other comparatorsof the comparators 102A-N to reduce power consumption by the ADC 100.For example, in a flash type of tracking ADC, only comparators with areference level close to a voltage level of the input signal, V_(in),may be turned on during normal operation. A control signal, CTRL, may beused to turn on and turn off the comparators 102A-N in this type of ADC.

Conventional tracking ADCs may also, for example, shuffle sensingcomponents of the ADC or manipulate the input signal, V_(in), to adaptthe tracking range of the ADC to improve tracking accuracy orresolution. For example, shuffling sensing components of the ADC mayinclude implementing a window tracking feature, which turns on a setnumber of the comparators 102A-N, such as four comparators, and thenshifts which four comparators are powered on based on a level of theinput signal, V_(in). In another example, adapting the tracking range ofthe ADC may include changing the reference level of the comparators102A-N, such as by varying a resistance of the resistors 104A-N.However, both of these conventional tracking ADCs have fixed numbers ofactive comparators of the comparators 104A-N. This reduces theflexibility of the ADC to respond to a rapidly changing input signal,V_(in), while also placing a limit of the power savings potential of thetracking ADC.

Shortcomings mentioned here are only representative and are includedsimply to highlight that a need exists for improved analog-to-digitalconverters (ADCs), particularly for consumer-level devices. Embodimentsdescribed here address certain shortcomings but not necessarily each andevery one described here or known in the art.

SUMMARY

A comparator tracking scheme for an analog-to-digital converter (ADC)may implement a dynamic window size by varying over time a number ofcomparators powered up to convert an analog input signal to a digitaloutput signal. Varying the number of activated comparators may allow theADC to increase the number of comparators when the analog input signalis rapidly changing to increase the accuracy of the digital outputsignal of the ADC. Varying the number of comparators powered up may alsoallow the ADC to decrease the number of comparators when the analoginput signal is relatively constant to decrease power consumption of theADC by reducing the number of powered up components. This dynamic windowsize may allow the ADC to improve the trade-off between powerconsumption and ability to capture rapidly changing signals in theanalog input signal.

A comparator-tracking scheme may be implemented, for example, in acontroller coupled to a plurality of comparators in an analog-to-digitalconverter (ADC). For example, the controller may determine a window sizefor the ADC and determine a window position for the ADC. The controllermay then activate comparators of the ADC within a window centered at thewindow position and having a width of the window size. In oneembodiment, the controller may determine a window size by analyzing anoutput of a filter, such as a band-pass filter (BPF) or a high-passfilter (HPF), coupled to either the analog input signal or the digitaloutput signal. When the filter output indicates a rapidly changinganalog input signal, the controller may dynamically increase a windowsize of the ADC, which may increase a number of comparators powered on.The controller may reevaluate the filter output and update the windowsize and/or window position at a later time. In one embodiment, thecontroller may continuously update the window size and/or windowposition.

According to one embodiment, an apparatus may include an analog inputnode configured to receive an analog signal; a plurality of comparatorscoupled to the analog input node and configured to convert the analogsignal to a digital signal; and/or a controller coupled to the pluralityof comparators. The controller may be configured to determine a windowsize for converting the analog signal; determine a window position forconverting the analog signal; turn on comparators of the plurality ofcomparators within a window defined by the determined window size andthe determined window position; and/or update the window size forconverting the analog signal.

In certain embodiments, the controller may also be configured to updatethe window size for converting the analog signal based, at least inpart, on a frequency input content of the digital signal; the controllermay also be configured to increase the window size when the frequencydetection block output is above a first threshold; the controller mayalso be configured to decrease the window size when the frequencydetection block output is below a second threshold; the controller mayalso be configured to increase the window size when the frequencydetection block detects a high magnitude of changes; the controller mayalso be configured to decrease the window size when the frequencydetection block detects a low magnitude of changes; and/or thecontroller may also be configured to update the window position from aprevious window position to a new window position by calculating acorrection value based, at least in part, on the frequency detectionblock output and adding the correction value to the previous windowposition to obtain the new window position.

In some embodiments, the apparatus may also include a frequencydetection block coupled to or integrated with the controller andconfigured to receive the digital signal, wherein the controller isconfigured to update the window size based, at least in part, on anoutput of the frequency detection block, wherein the frequency detectionblock may include a high-pass filter (HPF), wherein the high-pass filterhas a transfer function of approximately 1-z⁻¹, and/or wherein thefrequency detection block may include a band-pass filter (BPF).

According to another embodiment, a method may include converting ananalog signal to a digital signal with a plurality of comparators,wherein a first portion of the plurality of comparators are activatedand a second portion of the plurality of comparators are not activated,and wherein the first portion of comparators is defined by a window sizeand a window position; determining the window size for the first portionof comparators based, at least in part, on the digital signal, whereinthe window size determines a quantity of the plurality of comparators inthe first portion; determining the window position for the first portionof comparators based, at least in part, on the digital signal, whereinthe window position determines which of the plurality of comparators arein the first portion; and/or updating the window size for the firstportion of comparators.

In certain embodiments, the step of updating the window size may includeupdating the window size based, at least in part, on a frequency inputcontent of the digital signal; the step of adjusting the window size mayinclude decreasing the window size when a low magnitude of changes isdetected in the digital signal and increasing the window size when ahigh magnitude of changes is detected in the digital signal; the step ofdetecting the magnitude of changes may include performing high-passfiltering on the digital signal; the step of adjusting the window sizemay include increasing the window size when an output of the high-passfiltering is above a first threshold and decreasing the window size whenthe output of the high-pass filtering is below a second threshold;and/or the step of detecting the magnitude of changes may includeperforming band-pass filtering on the digital signal.

In some embodiments, the method may also include detecting a magnitudeof changes in the digital signal; adjusting the window size based on themagnitude of changes in the digital signal; and/or adjusting the windowposition from a previous window position to a new window position bycalculating a correction value based, at least in part, on the detectedfrequency changes in the digital signal and adding the correction valueto the previous window position to obtain the new window position.

According to a further embodiment, an apparatus may include a pluralityof comparators configured to convert an analog signal to a digitalsignal; a processing block coupled to receive the digital signal andconfigured to determine a frequency input content of the digital signal;and/or a controller coupled to the processing block and coupled to theplurality of comparators. The controller may be configured to determinea window size for converting the analog signal based, at least in part,on the frequency input content of the digital signal; determine a windowposition for converting the analog signal; turn on comparators of theplurality of comparators within a window defined by the determinedwindow size and the determined window position; and/or update the windowsize for converting the analog signal based, at least in part, on thefrequency input content of the digital signal.

In certain embodiments, the processing block may include a frequencydetection block; the processing block may include a high-pass filter(HPF) wherein the controller is configured to increase the window sizewhen the high-pass filter (HPF) output is above a first threshold anddecrease the window size when the high-pass filter (HPF) output is belowa second threshold; and/or the controller may include a digital outputtracking and prediction block configured to determine a portion of theplurality of comparators to activate and an analog-to-digital converter(ADC) control sequence block configured to generate a control sequenceto activate the portion of the plurality of comparators.

In some embodiments, the apparatus may also include a sparkle codecorrection block coupled to the digital signal output by the pluralityof comparators; and/or a thermocode decode block coupled to the sparklecode correction.

The foregoing has outlined rather broadly certain features and technicaladvantages of embodiments of the present invention in order that thedetailed description that follows may be better understood. Additionalfeatures and advantages will be described hereinafter that form thesubject of the claims of the invention. It should be appreciated bythose having ordinary skill in the art that the conception and specificembodiment disclosed may be readily utilized as a basis for modifying ordesigning other structures for carrying out the same or similarpurposes. It should also be realized by those having ordinary skill inthe art that such equivalent constructions do not depart from the spiritand scope of the invention as set forth in the appended claims.Additional features will be better understood from the followingdescription when considered in connection with the accompanying figures.It is to be expressly understood, however, that each of the figures isprovided for the purpose of illustration and description only and is notintended to limit the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the disclosed system and methods,reference is now made to the following descriptions taken in conjunctionwith the accompanying drawings.

FIG. 1 is a schematic of a conventional analog-to-digital converter(ADC).

FIG. 2A is a block diagram illustrating a control scheme for comparatorsof an analog-to-digital converter (ADC) having a first window sizeaccording to one embodiment of the disclosure.

FIG. 2B is a block diagram illustrating a control scheme for comparatorsof an analog-to-digital converter (ADC) having a second window sizeaccording to one embodiment of the disclosure.

FIG. 3 is a flow chart illustrating a method of dynamically controllinga window size of an analog-to-digital converter (ADC) according to oneembodiment of the disclosure.

FIG. 4 is a block diagram illustrating a controller with dynamic windowsize control of an analog-to-digital converter (ADC) according to oneembodiment of the disclosure.

FIG. 5 is a flow chart illustrating a method of adjusting a window sizeof an analog-to-digital converter (ADC) based on an output of ahigh-pass filter (HPF) according to one embodiment of the disclosure.

FIG. 6 is a block diagram illustrating a state machine for a dynamicwindow size in an analog-to-digital converter (ADC) according to oneembodiment of the disclosure.

FIG. 7 is a block diagram illustrating a change in window positionaccording to one embodiment of the disclosure.

FIG. 8 is a flow chart illustrating a method for adjusting a windowposition according to one embodiment of the disclosure.

DETAILED DESCRIPTION

A dynamic window size for an analog-to-digital converter (ADC) is shownconceptually in FIGS. 2A-2B. FIG. 2A is a block diagram illustrating acontrol scheme for comparators of an analog-to-digital converter (ADC)having a first window size according to one embodiment of thedisclosure. A plurality of comparators may each output one bit in adigital output signal, OUT. That is, bits 202A-N may each correspond tothe output of one comparator of an ADC. A control signal, CTRL, having anumber of bits may be provided to the plurality of comparators. Acomparator may activate when a bit of the control bits 204A-Ncorresponding to the comparator is ‘1.’ For example, control bits 204B-Eas shown in FIG. 2A are ‘1’ bits, and thus comparators corresponding tooutput bits 202B-E are activated. Although ‘1’ and ‘0’ bits are shown inthe control bits 204A-N, the values may be inverted such that a ‘0’ bitactivates the corresponding comparator. The ‘1’ control bits 204B-204Emay define a window 210 of active comparators. That is, the comparatorscorresponding to the output bits 202B-E within the window 210 are activeand powered on.

The control bits 204A-N may be generated by a controller coupled to thecomparators and the ADC. The controller may adjust the size of thewindow 210 by, for example, changing the control bits 204A-N. FIG. 2B isa block diagram illustrating a control scheme for comparators of ananalog-to-digital converter (ADC) having a second window size accordingto one embodiment of the disclosure. Control bits 204A-F are set as ‘1’bits by the controller to define an updated window 220. The window 220is two bits larger than the window 210. Thus, two additional comparatorsmay be activated by the control signal, CTRL. Although the window 220 isshown centered at the same position as the window 210, the position ofthe window 220 may also be changed during an update. For example, thewindow 220 may be shifted from control bits 204A-F to control bits204B-G. When the position of the window 220 is controlled along with thesize of the window 220, the size and position may be independentlycontrolled.

A dynamic window size may be implemented in an analog-to-digitalconverter (ADC) according to a method shown in FIG. 3. FIG. 3 is a flowchart illustrating a method of dynamically controlling a window size ofan analog-to-digital converter (ADC) according to one embodiment of thedisclosure. A method 300 begins at block 302 with determining a windowsize for an analog-to-digital converter (ADC). Then, at block 304 awindow position is determined for the ADC. The determined window sizeand position may define a window of active comparators, such as thewindows 210 and 220 of FIGS. 2A-B. At block 306, comparators of the ADCmay be activated corresponding to the determined window size of block302 and the determined window position of block 304. The comparators maybe activated by a control signal generated by the controller, such asthe control bits 204A-N of FIGS. 2A-B. At a later time, the determinedwindow size of block 302 may be updated at block 308 and the determinedwindow position of block 304 may be updated at block 310. The method 300of FIG. 3 may be executed, for example, within a controller coupled tothe ADC.

One example of a controller for controlling an analog-to-digitalconverter (ADC) is shown in FIG. 4. FIG. 4 is a block diagramillustrating a controller with dynamic window size control of ananalog-to-digital converter (ADC) according to one embodiment of thedisclosure. A system 400 may include a controller 410 coupled to an ADC404. The ADC 404 may include a plurality of comparators, which thecontroller 410 may instruct to activate (e.g., power on) or deactivate(e.g., power off). The ADC 404 may be coupled to an analog input node402 to receive an analog input signal, V_(in). The ADC 404 may output adigital signal, sig, that may be further processed by the controller 410to generate a digital output signal, OUT. For example, the controller410 may include a sparkle code correction block 412, which may correctbubble error, and a thermocode decode block 414, which may translate athermometer code to a two's complement code, to process the digitalsignal, sig, and generate the digital output signal, OUT. Althoughblocks of the controller 410 are shown as separate components of thecontroller 410, the blocks may be implemented in one or more controllersas part of one or more integrated circuits (ICs). The controllers or ICsmay, for example, be integrated into electronic devices, such as mobiledevices including cellular telephones and mobile audio players.

The controller 410 may also include a filter 416 coupled to the digitaloutput signal, OUT. The filter 416 may be, for example, a band-passfilter (BPF) or a high-pass filter (HPF). In one embodiment when thefilter 416 is a HPF, the filter 416 may have a transfer function of1-z⁻¹ and an update rate of approximately 0.5 MHz to 3 MHz. An output ofthe filter 416 may be provided to an ADC output tracking and predictionblock 418. The ADC output tracking and prediction block 418 may includea frequency detection block containing, for example, a logic circuit toprocess the output of the filter 416 and determine a frequency ofchanges within the analog input signal, V_(in). The ADC output trackingand prediction block 418 may also include logic circuitry fordetermining a window size and a window position based on informationfrom the filter 416 and current and previous outputs from the ADC 404.For example, the block 418 may receive data from the filter 416 and thesparkle code correction block 412 and generate a prediction of a futurevalue of the analog input signal, V_(in), and determine an appropriatewindow size and window position for the predicted future value of theanalog input signal, V_(in). The determined window size and windowposition may be output from the block 418 to an ADC control sequenceblock 420, which may convert the determined window size and windowposition into a control signal provided to the ADC 404. The outputcontrol signal from the ADC control sequence block 420 may be, forexample, the control bits 204A-N described above with reference to FIGS.2A-B.

When the filter 416 is a high-pass filter (HPF), the high-pass filtermay determine a magnitude of changes at the output digital signal, OUT,which are indicative of a magnitude of changes at the input analogsignal, V_(in). Thresholds may be set within the ADC output tracking andprediction block 418 to dynamically adjust a window size of the ADC 404based on an output of the high-pass filter (HPF). FIG. 5 is a flow chartillustrating a method of adjusting a window size of an analog-to-digitalconverter (ADC) based on an output of a high-pass filter (HPF) accordingto one embodiment of the disclosure. A method 500 may begin at block 502with determining if a high-pass filter output is higher than a firstthreshold. If the first threshold is exceeded, then the method 500 mayproceed to block 504 to increase a window size for the ADC 404. When thehigh-pass filter output is high, the analog input signal, V_(in), may berapidly changing. Thus, block 504 may correspond to increasing thewindow size when the frequency detection block of the ADC outputtracking and prediction block 418 detects a high magnitude of changes.

If the first threshold is not exceeded at block 502, then the method 500continues to block 506 to determine if an output of the high-pass filter(HPF) is below a second threshold. When the output is below the secondthreshold, the method 500 may proceed to block 508 to decrease a windowsize for the ADC 404. When the high-pass filter (HPF) output is belowthe second threshold, the analog input signal, V_(in), may be consideredto be relatively constant. Thus, block 508 may correspond to decreasingthe window size when the frequency detection block detects a lowmagnitude of changes. Decreasing the window size may decrease the numberof active comparators, and thus may decrease power consumption withinthe ADC 404. Reduced power consumption may be advantageous in smalldevices where little space for heat dissipation is available. Reducedpower consumption may also be advantageous in portable devices to extendbattery life. After increasing or decreasing the window size at blocks504 and 508, respectively, the method 500 may return to block 502 tocontinue to update the window size. If no change is made in the windowsize at block 506, the method 500 may return to testing the output ofthe high pass filter (HPF) at block 502.

The increasing and decreasing of the window size at blocks 504 and 508may be implemented in a state machine. In the state machine, the firstthreshold and the second threshold for increasing or decreasing thewindow size, respectively, may be adjusted based on a current state ofthe state machine. FIG. 6 is a block diagram illustrating a statemachine for a dynamic window size in an analog-to-digital converter(ADC) according to one embodiment of the disclosure. A state machine 600may include, for example, state 602 corresponding to a window size offour comparators, state 604 corresponding to a window size of sixcomparators, and state 606 corresponding to a window size of eightcomparators. Although only three example states 602, 604, and 606 areshown, additional larger or small window sizes may be included in thestate machine 600. Additionally, increments of window size of sizesother than two are also possible within the state machine 600. The statemachine 600 may be updated, that is to determine whether to transitionbetween states 602, 604, and 606, once per clock cycle. In oneembodiment described above, the clock cycle may be approximately 0.5 MHzto 3 MHz.

The state machine 600 may begin, for example, in state 602 with a windowsize of four. When the output of a high-pass filter (HPF) is greaterthan two, the state machine 600 may transition to state 604 with awindow size of six. The high-pass filter (HPF) may produce a number ofdifferent outputs used to determine the content of the data. In oneembodiment, the high-pass filter (HPF) output may be a discrete valueindicating a relative magnitude of a change of the signal. For example,the value ‘2’ corresponding to transition between the state 602 and 604may indicate a certain magnitude of change in the signal passing throughthe high-pass filter (HPF). At state 604, the first threshold may be setto three and the second threshold may be set to one. When the output ofthe high-pass filter (HPF) is greater than or equal to three, the statemachine 600 may transition to a state 606 with a window size of eight.When the output of the high-pass filter (HPF) is less than or equal toone, the state machine 600 may return to state 602 with a window size offour. A generic state machine, similar to that of state machine 600, maybe formulated from an equation for window size:

${{W(n)} = {{W\left( {n - 1} \right)} + \Delta}},{\Delta = \left\{ {\begin{matrix}{2,\;{{{{if}\mspace{14mu}{high}} - {{pass}\mspace{14mu}{filter}\mspace{14mu}{output}}} \geq {Threshold}_{1}}} \\{0,\;{{{{if}\mspace{14mu}{high}} - {{pass}\mspace{14mu}{filter}\mspace{14mu}{output}}} < {Threshold}_{2}}} \\{{- 2},\;{{{{if}\mspace{14mu}{high}} - {{pass}\mspace{14mu}{filter}\mspace{14mu}{output}}} < {Threshold}_{3}}}\end{matrix},} \right.}$where W(n) is a current window size, W(n−1) is a previous window size,and Threshold₁, Threshold₂, and Threshold₃ are thresholds for changingthe dynamic window size. The threshold values may change as the windowsize changes. For example, in state 602, Threshold₁ may be 2 andThreshold₃ may be 1, and in state 604, Threshold₁ may be 3 andThreshold₃ may be 1.

As described above, a window size may be dynamically adjusted. A windowposition may also be dynamically adjusted independently of the windowsize. A change in window position is shown conceptually in FIG. 7. FIG.7 is a block diagram illustrating a change in window position accordingto one embodiment of the disclosure. A window 702 may initially bepositioned around bits n, n−1, n−2, n−3, n−4, and n−5. The correspondingoutput bits of digital output signal, OUT, may be 0, 0, 0, 1, 1, and 1,respectively. In one embodiment, the window position may be selected toposition a transition from 0's to 1's of the digital output signal, OUT,at a center of the window 702. In other embodiments, the window positionmay be selected to position a transition from 0's to 1's to provideadditional headroom in the direction a signal is changing. For example,when the transition from 0's to 1's is expected to move toward lesssignificant bits (LSBs, e.g., right in the bits of FIG. 7), the windowposition may be selected to place the transition from 0's to 1's towardmore significant bits (MSBs, e.g., left in the bits of FIG. 7). A newwindow position may be determined and the window 702 shifted to a window704 including bits n−2, n−3, n−4, n−5, n−6, and n−7. As shown in FIG. 7,the window size of windows 702 and 704 are identical. However, a changein window size may also occur when the window position changes.

Window position control may be programmed into the controller 410 ofFIG. 4. One method for adjusting a window position by the controller isshown in FIG. 8. FIG. 8 is a flow chart illustrating a method foradjusting a window position according to one embodiment of thedisclosure. A method 800 may start at block 802 with receiving ahigh-pass filter (HPF) output. At block 804, a correction value may bedetermined based on the received HPF output at block 802. The correctionvalue may be, for example, a delta difference value indicating an amountand direction to shift the window position. Then, at block 806, thecorrection value may be added to a current window position of theanalog-to-digital converter (ADC). In one example, a new window positionmay be calculated according to:Position(k)=Position(k−1)+Δ,where Δ is the correction value, Position(k−1) is a previous windowposition, and Position(k) is a new window position.

If implemented in firmware and/or software, the functions describedabove may be stored as one or more instructions or code on acomputer-readable medium. Examples include non-transitorycomputer-readable media encoded with a data structure andcomputer-readable media encoded with a computer program.Computer-readable media includes physical computer storage media. Astorage medium may be any available medium that can be accessed by acomputer. By way of example, and not limitation, such computer-readablemedia can comprise RAM, ROM, EEPROM, CD-ROM or other optical diskstorage, magnetic disk storage or other magnetic storage devices, or anyother medium that can be used to store desired program code in the formof instructions or data structures and that can be accessed by acomputer. Disk and disc includes compact discs (CD), laser discs,optical discs, digital versatile discs (DVD), floppy disks and blu-raydiscs. Generally, disks reproduce data magnetically, and discs reproducedata optically. Combinations of the above should also be included withinthe scope of computer-readable media.

In addition to storage on computer readable medium, instructions and/ordata may be provided as signals on transmission media included in acommunication apparatus. For example, a communication apparatus mayinclude a transceiver having signals indicative of instructions anddata. The instructions and data are configured to cause one or moreprocessors to implement the functions outlined in the claims.

Although the present disclosure and certain representative advantageshave been described in detail, it should be understood that variouschanges, substitutions and alterations can be made herein withoutdeparting from the spirit and scope of the disclosure as defined by theappended claims. For example, although activation of comparators in ananalog-to-digital converter (ADC) is described above, other componentsmay be controlled with the controller described above and/or comparatorsfor purposes other than analog-to-digital conversion may be controlledwith the controller described above. Moreover, the scope of the presentapplication is not intended to be limited to the particular embodimentsof the process, machine, manufacture, composition of matter, means,methods and steps described in the specification. As one of ordinaryskill in the art will readily appreciate from the present disclosure,processes, machines, manufacture, compositions of matter, means,methods, or steps, presently existing or later to be developed thatperform substantially the same function or achieve substantially thesame result as the corresponding embodiments described herein may beutilized. Accordingly, the appended claims are intended to includewithin their scope such processes, machines, manufacture, compositionsof matter, means, methods, or steps.

What is claimed is:
 1. An apparatus, comprising: an analog input nodeconfigured to receive an analog signal; a plurality of comparatorscoupled to the analog input node and configured to convert the analogsignal to a digital signal; a frequency detection block configured toreceive the digital signal and analyze a frequency content of thedigital signal; and a controller coupled to the plurality of comparatorsand to the frequency detection block, wherein the controller isconfigured to: dynamically determine a window size for converting theanalog signal based, at least in part, on an output of the frequencydetection block, wherein determining the window size comprises:increasing the window size when the frequency detection block detects ahigh magnitude of changes; and decreasing the window size when thefrequency detection block detects a low magnitude of changes; determinea window position for converting the analog signal; and turn oncomparators of the plurality of comparators within a window defined bythe determined window size and the determined window position.
 2. Theapparatus of claim 1, wherein the controller is further configured toupdate the window size for converting the analog signal by dynamicallydetermining a second window size for converting the analog signal. 3.The apparatus of claim 1, wherein the frequency detection blockcomprises a high-pass filter (HPF).
 4. The apparatus of claim 3, whereinthe high-pass filter (HPF) has a transfer function of approximately1-z⁻¹.
 5. The apparatus of claim 1, wherein the frequency detectionblock comprises a band-pass filter (BPF).
 6. The apparatus of claim 1,wherein the controller is further configured to: increase the windowsize when the frequency detection block output is above a firstthreshold; and decrease the window size when the frequency detectionblock output is below a second threshold.
 7. The apparatus of claim 1,wherein the controller is configured to increase the window size byturning on additional comparators of the plurality of comparators, andwherein the controller is configured to decrease the window size byturning off comparators of the plurality of comparators.
 8. Theapparatus of claim 1, wherein the controller is further configured todynamically determine the window position from a previous windowposition to a new window position by: calculating a correction valuebased, at least in part, on the frequency detection block output; andadding the correction value to the previous window position to obtainthe new window position.
 9. A method, comprising: converting an analogsignal to a digital signal with a plurality of comparators, wherein afirst portion of the plurality of comparators are activated and a secondportion of the plurality of comparators are not activated, and whereinthe first portion of comparators is defined by a window size and awindow position; dynamically determining the window size for the firstportion of comparators based, at least in part, on the digital signal,wherein the window size determines a quantity of the plurality ofcomparators in the first portion, wherein the step of dynamicallydetermining the window size comprises: detecting a magnitude of changesin the digital signal; and adjusting the window size based on themagnitude of changes in the digital signal by: decreasing the windowsize when a low magnitude of changes is detected in the digital signal;and increasing the window size when a high magnitude of changes isdetected in the digital signal; and determining the window position forthe first portion of comparators based, at least in part, on the digitalsignal, wherein the window position determines which of the plurality ofcomparators are in the first portion.
 10. The method of claim 9, furthercomprising updating the window size for the first portion of comparatorsby dynamically determining a second window size.
 11. The method of claim9, wherein the step of updating the window size comprises dynamicallydetermining the window size based, at least in part, on a frequencyinput content of the digital signal.
 12. The method of claim 9, whereinthe step of decreasing the window size comprises turning off comparatorsof the plurality of comparators, and wherein the step of increasing thewindow size comprises turning on comparators of the plurality ofcomparators.
 13. The method of claim 9, wherein the step of detectingthe magnitude of changes comprises performing high-pass filtering on thedigital signal.
 14. The method of claim 13, wherein the step ofadjusting the window size comprises: increasing the window size when anoutput of the high-pass filtering is above a first threshold; anddecreasing the window size when the output of the high-pass filtering isbelow a second threshold.
 15. The method of claim 9, wherein the step ofdetecting the magnitude of changes comprises performing band-passfiltering on the digital signal.
 16. The method of claim 9, furthercomprising adjusting the window position from a previous window positionto a new window position by: calculating a correction value based, atleast in part, on the detected frequency changes in the digital signal;and adding the correction value to the previous window position toobtain the new window position.
 17. An apparatus, comprising: aplurality of comparators configured to convert an analog signal to adigital signal; a processing block configured to receive the digitalsignal and configured to determine a frequency input content of thedigital signal, wherein the processing block comprises a frequencydetection block; and a controller coupled to the processing block andcoupled to the plurality of comparators, wherein the controller isconfigured to: dynamically determine a window size for converting theanalog signal based, at least in part, on an indication of the frequencyinput content of the digital signal received from the processing block,wherein determining the window size comprises: increasing the windowsize when the processing block detects a high magnitude of changes; anddecreasing the window size when the processing block detects a lowmagnitude of changes; determine a window position for converting theanalog signal; and turn on comparators of the plurality of comparatorswithin a window defined by the determined window size and the determinedwindow position.
 18. The apparatus of claim 17, further comprising: asparkle code correction block coupled to the digital signal output bythe plurality of comparators; and a thermocode decode block coupled tothe sparkle code correction.
 19. The apparatus of claim 17, wherein theprocessing block comprises a high-pass filter (HPF), and wherein thecontroller is configured to: increase the window size when the high-passfilter (HPF) output is above a first threshold; and decrease the windowsize when the high-pass filter (HPF) output is below a second threshold.20. The apparatus of claim 19, wherein the controller is configured toincrease the window size by turning on comparators of the plurality ofcomparators, and wherein the controller is configured to decrease thewindow size by turning off comparators of the plurality of comparators.21. The apparatus of claim 17, wherein the controller comprises: adigital output tracking and prediction block configured to determine aportion of the plurality of comparators to activate; and ananalog-to-digital converter (ADC) control sequence block configured togenerate a control sequence to activate the portion of the plurality ofcomparators.